Computer programmes comprising executable programme code may be executed by at least one processing unit of a processor system. The execution of the programme code may be accelerated by using a hierarchical memory architecture comprising several memory resources providing different access times. Code and data portions of the executable programme code may be loaded into a memory resource having a small access time. The memory resource having the small access time may be called cache and loading code and data portions into said cache may be called caching.
A further possibility to accelerate the execution of programme code may be a parallelisation by using a plurality of processing units that execute instructions of the programme code parallel to each other. A processor system comprising a plurality of processing units may be called multiprocessor system. Each of said plurality of processing units may access to a specific cache that is exclusively related to a specific processing unit. This may, for example, be realised by providing a first cache that is exclusively dedicated to a first processing unit and a second cache that is exclusively dedicated to a second processing unit. However, the result of the executed programme code has to provide predictable results that are independent from the parallelisation, e.g., the number of processing units. Therefore, the caches of the plurality of processing units of the processor system must be cache-coherent, e.g., the cached data/instructions have to be consistent when used for a calculation. Providing cache coherence may require the alteration of the first cache of the first processing unit due to a change within the second cache of the second processing unit. In this way, a failure within the second processing unit may affect the first processing unit due to the cache coherence of the multiprocessor system. A multiprocessor system that is kept cache-coherent may be called a cache-coherent multiprocessor system.
In safety critical applications, e.g., according to ISO 26262, IEC 61508, or EN 50128/9, one common approach for reaching given safety requirements is to execute two instances of software on different processing units, wherein both instances execute basically similar programme codes. The results are compared to detect failures in the processing units. However, a failure in a processing unit may spread through the whole processor system due to the coherency of the shared memory resource when a cache-coherent multiprocessor system is used.
Hattendorf A., Raabe A., Knoll A., “Shared Memory Protection for Spatial Separation in Multicore Architectures”, Industrial Embedded Systems (SIES), 2012, 7th IEEE International Symposium on, pp 299-302, 20-22 Jun. 2012 describes different architectures of multi-core computer systems using memory protection units (MPU) or memory management units (MMU). The advantages and draw-backs of the mentioned architectures are summarized.
Nam Ho, Anh-Vu Dinh-Duc, “A Hardware/Software Approach to Detect Memory Corruptions in Embedded Systems”, Advanced Technologies for Communications (ATC), 2010 International Conference on, pp 285-290, 20-22 Oct. 2010 describes a method to detect memory corruptions in a debugging phase at run-time for embedded systems without a MMU.